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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\Applications\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SERDES_IP\IPlib\PCIE\data\pcie_controller_encrypt.v<br>
D:\Applications\Gowin\Gowin_V1.9.11.01_x64\IDE\ipcore\SERDES_IP\IPlib\PCIE\data\pcie_controller_top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.11.01 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5AST-LV138PG484AC1/I0</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5AST-138</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>B</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Mar 11 19:07:33 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>PCIE_Controller_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.633s, Peak memory usage = 139.730MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.14s, Peak memory usage = 139.730MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 139.730MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 139.730MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 139.730MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.254s, Peak memory usage = 145.254MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 145.406MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 145.406MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 145.406MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>2316</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>1619</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>775</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>844</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>44</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>18</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>24</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>20</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>10</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>14</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>3</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>37(23 LUT, 14 ALU) / 138240</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>44 / 139095</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 139095</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>44 / 139095</td>
<td><1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 340</td>
<td>0%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>1</td>
<td>pcie_tl_clk_i</td>
<td>Base</td>
<td>10.000</td>
<td>100.000</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>pcie_tl_clk_i</td>
<td>100.000(MHz)</td>
<td>323.756(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.101</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s3/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s3/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s1/CLK</td>
</tr>
<tr>
<td>10.101</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.158, 41.674%; route: 1.238, 44.555%; tC2Q: 0.382, 13.771%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.159</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.190</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n27_s2/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n27_s2/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_6_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_6_s1/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_6_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.158, 41.674%; route: 1.238, 44.555%; tC2Q: 0.382, 13.771%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.170</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.179</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n31_s3/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n31_s3/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n30_s2/I1</td>
</tr>
<tr>
<td>2.766</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n30_s2/F</td>
</tr>
<tr>
<td>3.179</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_3_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_3_s1/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_3_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.170</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.179</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n29_s3/I1</td>
</tr>
<tr>
<td>2.766</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n29_s3/F</td>
</tr>
<tr>
<td>3.179</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_4_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_4_s1/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_4_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.170</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.179</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>pcie_tl_clk_i[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_1_s1/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_7_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n28_s2/I1</td>
</tr>
<tr>
<td>2.766</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/n28_s2/F</td>
</tr>
<tr>
<td>3.179</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_5_s1/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>pcie_tl_clk_i</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>pcie_tl_clk_i_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>44</td>
<td>pcie_tl_clk_i_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_5_s1/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>u_pcie_controller/u_pcie_linkup/cnt_5_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.146, 41.437%; route: 1.238, 44.736%; tC2Q: 0.382, 13.827%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
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